Micron details G11 memory chips with roughly double the storage density

Micron Technology outlined specifications for its upcoming G11 generation of 3D NAND flash memory, saying production will ramp in the second half of 2027. The company said at an event this week that the new memory will deliver about twice the storage density of its current technology, along with faster input and output performance and lower power consumption.

In triple-level-cell form, density would rise from roughly 21 Gb per square millimeter in the current G9 generation to about 42 Gb per square millimeter. Micron projects input and output speeds increasing by up to 50%, moving from 3,600 MT/s to 5,400 MT/s, while the energy used to transfer each bit should fall by more than 25%. The company positions the density figure above competing next-generation NAND products from Kioxia, called BiCS10, and Samsung, called V10.

The chips are intended for high-capacity SSDs in client computers and data centers, as well as storage devices built for artificial intelligence workloads, which require greater bandwidth and better energy efficiency.

G11 introduces wafer-on-wafer bonding, an approach already used by Chinese competitor YMTC. The method allows Micron to build the NAND array and the peripheral circuitry on separate wafers, each manufactured with a process suited to its function, before bonding the two together. Micron has used CMOS-under-array designs for several generations, but bonding allows the memory array and logic to be optimized independently.

Scott DeBoer, Micron's president and chief technology and products officer, said the company had previously committed to introducing the technology when it became cost-effective and relevant to product specifications. "This is the right timing for that technology," DeBoer said, describing G11 as "the world's most advanced NAND" and confirming it relies on wafer-on-wafer bonding.

G11 will exceed 400 layers, though Micron has not disclosed the exact count of active wordline layers or memory decks. The company says the design will have an industry-leading memory cell pitch, indicating the density gain comes from both additional layers and smaller cell dimensions. Micron plans to release more technical details in 2027, ahead of high-volume production.