Chinese Chipmakers Face Steep Cost Climb Bypassing EUV Restrictions

Chinese semiconductor manufacturers are finding workarounds for the ban on extreme ultraviolet lithography machines, but the financial and technical costs rise with every additional exposure step. While export controls keep ASML's EUV equipment out of the country, local firms rely on deep ultraviolet tools to produce advanced silicon. Industry experts indicate that this method creates more opportunities for defects and extends production timelines.

The reliance on older equipment stems from the fact that ASML is the sole producer of EUV machines, which use 13.5nm-wavelength light for high-precision printing. Analysts estimate the resulting gap between China and Western peers at five years or more. Despite this handicap, Chinese firms have achieved notable progress. A 2023 analysis of the Huawei Mate 60 Pro revealed that SMIC produced the Kirin 9000S processor on a 7nm-class process without EUV. Recent evaluations suggest the newer Kirin 9030 brings SMIC's DUV process closer to 5nm density, although it still lags behind TSMC and Samsung.

The core technique involves multiple patterning, where a single complex layer is split into several simpler patterns and built up sequentially. Chris Mack, co-founder and CTO of Fractilia, notes that this approach ignores trade-offs. He states that industry standards suggest three exposures on a 193 immersion tool cost roughly the same as one EUV exposure. However, at four masks, EUV becomes the more economical choice.

Precision issues compound with each additional step. Every new pattern must align perfectly with previous etchings, leading to accumulated overlay errors. Designers often add space around features to compensate, which enlarges the chip and reduces the number of dies per wafer. Mack emphasizes that manufacturers sell dies, not wafers, making this a costly inefficiency when wafers cost tens of thousands of dollars.

Memory production provides clear evidence of this efficiency gap. A June report from Morgan Stanley estimated that Chinese DRAM maker CXMT produces only one-third as many bits per wafer as Western rivals. The bank described lithography access as a hard ceiling for Chinese memory development. Mack added that node labels like 5nm or 3nm have limited standalone meaning, and SMIC's N+3 process remains less scaled than established 5nm processes from major competitors.

DUV technology still has room for advancement. Micron developed its 1-alpha DRAM without EUV using tight process control. Morgan Stanley believes CXMT's planned move to 1-alpha DRAM for HBM3e is achievable without EUV. Douglas Fuller of Copenhagen Business School expects advanced packaging to allow DUV use for the latest DRAM generations by the end of the decade. Mack noted that China could advance further with a full 193 immersion ecosystem, though he stressed that memory is easier than logic.

Micron eventually adopted EUV for its 1-gamma DRAM, claiming more than 30% greater bit density than the previous 1-beta generation. While EUV has its own drawbacks, such as stochastic effects, Mack said he would be hard pressed to believe a 3nm or 2nm node could be economically viable without it. Chinese chipmakers can continue pushing DUV by accepting larger dies, poorer yields, or longer manufacturing times. Morgan Stanley projects CXMT will increase its global DRAM bit supply share from 14% in 2026 to 16% in 2028 through new capacity. The bank also expects China's AI chip self-sufficiency to rise from 42% in 2025 to 70% by 2030.